The present invention relates to the testing of integrated circuits, and in particular, to the electrical characterization of a chip scale package.
Electrical components utilizing integrated circuit chips are used in a number of applications. Controlled Collapsed Chip Connection is an interconnect technology developed as an alternative to wire bonding. This technology is generally known as C4 technology, or flip chip packaging. Broadly stated, one or more integrated circuit chips are mounted above a single or multiple layer substrate and pads on the chip are electrically connected to corresponding pads on a substrate by a plurality of electrical connections, such as solder bumps. The integrated circuit chips may be assembled in an array such as a 10xc3x9710 array. A substrate is then electrically connected to another electronic device such as a circuit board with the total package being used in an electronic device such as a computer.
It is desirable to perform an electrical characterization of an integrated circuit by measuring inductance (L), capacitance (C), and resistance (R) at electrical contacts of the integrated circuit. This has presented a problem, however, when measuring these parameters for a xe2x80x9cchip scale package.xe2x80x9dSemiconductor dice, or chips, are typically individually packaged for use in plastic or ceramic packages. This is sometimes referred to as the first level of packaging. The package is required to support, protect, and dissipate heat from the die and to provide a lead system for power and signal distribution to the die. The package is also useful for performing burn-in and functionality testing of the die.
One type of semiconductor package is referred to as a xe2x80x9cchip scale package.xe2x80x9d Chip scale packages are also referred to as xe2x80x9cchip size packages,xe2x80x9d and the dice are referred to as being, xe2x80x9cminimally packaged.xe2x80x9d Chip scale packages can be fabricated in xe2x80x9cuncasedxe2x80x9d or xe2x80x9ccasedxe2x80x9d configurations. Uncased chip scale packages have a footprint that is about the same as an unpackaged die. Cased chip scale packages have a peripheral outline that is slightly larger than an unpackaged die. For example, a footprint for a typical cased chip scale package can be about 1.2 times the size of the die contained within the package.
Typically, a chip scale package includes a substrate bonded to the face of the die. The substrate includes the external contacts for making outside electrical connections to the chip scale package. The substrate for a chip scale package can comprise flexible material, such as a polymer tape, or a rigid material, such as silicon, ceramic, or glass. The external contacts for one type of chip scale package includes solder balls arranged in a dense array, such as a ball grid array xe2x80x9cBGA,xe2x80x9d or a fine ball grid array xe2x80x9cFBGA.xe2x80x9d These dense arrays permit a high input/output capability for the chip scale package. For example, a FBGA on a chip scale package can include several hundred solder balls.
In order to test the electrical characteristics of the integrated circuit, test probes are used to contact individual solder balls. Performing precise measurements of the electrical characteristics on a chip scale package is very difficult, however, due to the dimensions. It is hard to isolate a single solder ball or other electrical contact, while grounding the remainder of the solder balls. Hence, isolation and testing of a single, selected solder ball of an integrated circuit has proven to be a difficult task.
There is a need for a test fixture that is able to isolate a single electrical contact (e.g., solder ball) on a chip scale package, while grounding all of the remaining solder balls on the chip scale package. Such a test fixture permits proper isolation of the solder ball under test for determining electrical characteristics at the solder ball.
These and other needs are met by embodiments of the present invention which provide a test fixture for holding, for electrical characteristic testing, an integrated circuit chip having a plurality of electrical contacts. This test fixture comprises a base, an isolation plate, and a holding device configured to hold the isolation plate against the base with an integrated circuit under test between the base and the isolation plate. The isolation plate is configured to contact and ground all of the plurality of electrical contacts of the integrated circuits under test, except for a selected subset of the electrical contacts.
By providing an isolation plate, that contacts and grounds all of the plurality of electrical contacts, except for a selected subset of these contacts, a single electrical contact may be isolated for electrical characteristic testing. Hence, electrical characteristics of a chip scale package may be adequately tested.
The earlier stated needs are also met by another embodiment of the present invention which provides a method of isolating an electrical contact of a chip scale package for testing the electrical characteristics at the electrical contact. This method comprises the steps of positioning a chip scale package to expose all of the electrical contacts of the chip scale package, and placing a conductive plate on the chip scale package. This plate is placed so that the plate contacts all of the electrical contacts except for a selected subset of the electrical contacts. The conductive plate is grounded to thereby ground all of the electrical contacts except for the selected substrate. The selected subset is exposed to allow testing of the electrical characteristics at the selected subset.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.